1. Field of the Invention
The present relates to the design and manufacture of semiconductor devices. More particularly, the present invention relates to improved techniques for detecting etch endpoints in metal fuse fabrication.
2. Description of the Related Art
There are a significant number of integrated circuit applications that require some sort of programmable memory for storing information. A common way of programmably storing data on an integrated circuit chip is to design what are known as "metal fuses." Metal fuses are typically patterned from existing metallization layers that are fabricated over dielectric layers of a silicon wafer. By way of example, after a metallization layer is deposited over a dielectric layer, a spin-coating process is used to apply a photoresist over the metallization layer.
The photoresist layer is then patterned with a reticle-stepper apparatus, which is used to transfer a desired pattern to the photoresist layer. Once patterned (i.e., exposed and developed), the photoresist will resemble a mask that leaves exposed certain regions of the underlying metallization, while still covering other portions of the metallization layer. Next, an etching operations is performed to remove portions of the metallization layer where the photoresist was not present. At this point, the metallization layer will have been patterned to define any number of features, such as interconnection lines and metal fuse structures. The metallization layer may then be covered with a dielectric layer, and terminal via (TV) holes etched down close to the metal fuse structures. However, in metal fuse technology, there is a general requirement that a certain thickness of dielectric layer remain over the metal fuse structure to ensure appropriate functionality.
A common problem in etching the terminal vias is that the amount of dielectric material overlying the metal fuse structures varies in thickness depends on the type of deposition technique used, the location of neighboring features and the region of the wafer being patterned. As a result, the timed etching processes have to be varied to take into account these and other factors. Unfortunately, such variations in the formation of the terminal vias may translate into substantial losses in productivity as well as damaged metal fuse structures. That is, if the terminal via etching operation removes too much of the overlying dielectric, or etches down into the metallization layer, the metal fuse structure may become too damaged to work for its intended purpose.
With this in mind, FIG. 1 shows a cross-sectional view of a semiconductor wafer 100 having a number of layers fabricated thereon. As shown, a dielectric layer 102 is commonly deposited over the semiconductor wafer 100 to a thickness that sufficiently insulates any active devices patterned throughout the semiconductor wafer 100. Once the dielectric layer 102 has been deposited, a metallization layer is formed over the dielectric layer 102 and patterned in the aforementioned method to form a metallization feature 104.
In this example, the metallization feature 104 is fabricated in the form of a metal fuse structure that may be programmed to store bit data or interconnect devices. In a next step, an oxide layer 106 is deposited over the metallization feature 104, as well as over other features throughout the semiconductor wafer. As mentioned above, it is a common requirement that an amount of oxide, e.g., to a level 120 remain over the metallization feature 104 to enable appropriate programming. In typical cases, the level 120 of oxide that remains should range between about 1,000 angstroms and 3,000 angstroms.
Of course, if the underlying metallization feature 104 (which may be a metal fuse structure) becomes exposed, the programming integrity of the metal fuse structure will suffer due to the inability to control the trench via etching operation over varying oxide thicknesses. Although fuse designers typically implement timed etching techniques, the timing parameters vary with oxide thicknesses. As such, the timing techniques will many times fail to accurately detect a desired end-point when performing terminal via etching.
In view of the foregoing, there is a need for a method and apparatus for forming terminal vias in metal fuse structures without over-etching overlying oxide materials. There is also a need for metal fuse structures that improve stress migration problems in underlying metallization layers.